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The SiP (System in Package) Consortium is an organization aimed at efficient development of next generation SiP, and is primarily involved with the materials equipments and passive components manufacturers who form the foundation of the semiconductor packaging process. Since each of these companies can offer cutting edge technology in its field, the Consortium's SiP development is able to achieve technology worthy of "#1 Technology Worldwide" status. The SiP Consortium was established to leverage the synergy produced by the cooperation of companies in varied industries, to provide more advanced technological resources and more sophisticated development. Moving forward, the SiP Consortium will focus on the following issues:
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Activism for the maintenance of SiP technology infrastructure/Seminars/Promotion
of Defacto Standards |
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SiP technology development (development of SiP parts, materials,
device technologies) |
 Officers
| Chairman |
Kawanishi Tsuyoshi |
(President, TEK Consulting) |
| Vice Chairman |
Suga Tadakazu |
(Professor, The University of Tokyo, School of Engineering,
Dept. Precision Engineering Microsystem Integration
&
Packaging Laboratories) |
| Technical Director |
Shinya Sasayama |
(Professor of Technology Development Management,TOKYO UNIVERSITY OF SCIENCE) |
| Director General |
Fujitsu Takao |
(President and Representative Director, J-SiP
Corporation) |
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| Organizational Chart |
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| A Message from the Director General |
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Since its inception in August
of 2002, the SiP Consortium has been steadily advancing
its original goal of developing technology essential to building
SiP infrastructure. This has been made possible with the cooperation
of its members- Chairman Kawanishi, Vice Chairman Suga, the
solid backup of the Advisor Committee comprised of top-level
representatives from member companies, the Consortium Operating
Committee, and the Technology development Division members. |
The infrastructure for SMT packaging technology, that makes use of
reflow soldering as a 2-dimensional packaging technology, has evolved
over the past 20 years. Improvements and standardization of Pick &
Place mounters, refinement and standardization of PCB design, miniaturization
and standardization of parts included semiconductor packaging, and
advanced standardization of SMT packaging infrastructure all provide
evidence of the maturity of this field. It is because of the parts,
materials, and devices that are built on this infrastructure, that
electronic devices can be manufactured at low costs with uniformity,
whether packaged in Japan, China, or elsewhere. Although the refinement
and miniaturization of SMT infrastructure has steadily improved over
the years, it is beginning to approach its technical limit.
The new packaging infrastructure that the SiP Consortium is
proposing aims to create packaging technology that enables miniaturized
and refined 3-dimensional packaging, based on semiconductor packaging
technology. We can expect the emergence of products that require ultra-small,
high-density 3-dimensional packaging that is difficult to achieve
with the highly mature 2-dimensional SMT packaging technology. Furthermore,
demand for such a technology is likely to increase.
It is the objective of this Consortium to deliver one after another,
the parts, materials, and devices needed in an infrastructure for
3-dimensional packaging of electronic devices used in such products
as small robots, sensors, and other MEMS devices. All of our participating
companies are working to realize this goal, one step at a time.
Since the development of such a new infrastructure requires the integration
of many technologies, the Consortium plans to hold semiannual seminars,
to evangelize about the benefits of SiP, and attract the participation
of many engineers.
It is our hope that through the dissemination of information on this
Web Site, you will gain an interest in SiP, feel strongly about this
new infrastructure, and actively communicate to use any ideas or desires
that you may have.
We will work to make this Web site a favorite among the many engineers
who work with SIP, who will use it as a reference for SIP related
materials, and as a web forum. This site is an important piece of
the Consortium's endeavors. Please enjoy it. |
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| Contact Information |
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7F Shin-Yokohama Tosho Building #3
3-9-5 Shin-Yokohama
Kohoku-ku, Yokohama
222-0033 JAPAN
| TEL |
: 045-474-4313 |
| FAX |
: 045-474-4314 |
[Access]
5 min. walk from JR Shin-Yokohama Station (North exit)
Looking ahead, we plan to use this Web site to
both collect and circulate information about SiP, and aggressively
promote "Activism for the maintenance of SiP technology infrastructure/Seminars/Promotion
of Defacto Standards", as well as the development of SiP parts,
materials, and device technology that support SiP. |
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